In a CMOS circuit constituting an inverter circuit, a NAND circuit, or the like including field effect transistors in related art, a p-channel type field effect transistor and an n-channel type field effect transistor are apposed. Additionally, development is made to achieve higher density of a gate and lower power consumption by scaling down such a layout. However, processing difficulty is increased, and a manufacturing cost is largely increased.
For a low power consumption device, a tunnel field effect transistor (TFET) can be exemplified as a candidate of a next generation device. Here, two-dimensional materials (2D materials) such as transition metal dichalcogenides (TMDC) are focused in development of the TFET. Additionally, such a TFET is known from Japanese Patent Application Laid-open No. 2015-090984, for example. In a semiconductor element disclosed in this patent publication includes:
a semiconductor layer that includes a two-dimensional substance element including: a first two-dimensional substance containing a first metal chalcogenide-based substance; and a second two-dimensional substance linked to a side surface of the first two-dimensional substance and containing a second metal chalcogenide-based substance, the first two-dimensional substance and the second two-dimensional substance being chemically bonded; and
at least one non-semiconductor layer located on at least one surface semiconductor layer.